Traditional programmable integrated circuits (ICs) such as Complex PLDs (CPLDs) and Field Programmable Gate Arrays (FPGAs) typically use millions of Static Random Access Memory (SRAM) configuration memory cells to program the functionality of the implemented circuit. The configuration memory cells may be those for programming interconnect, logic, or memory resources of the programmable IC, for example.
The presence of an increasing number of SRAM configuration memory cells in programmable ICs, with chip geometries becoming smaller and supply voltages becoming lower, increases the likelihood that the configuration memory cell storage state could be upset due to collisions with cosmic particles from outer space or alpha particles from IC packaging materials. The unexpected change in state of a memory cell is referred to as a single event upset (SEU). With SEUs more likely to occur, the mean time to failure for a particular program configuration for the PLD will decrease and the failures in time (FIT) rate will increase.